Silicon is the material of choice for the fabrication of ultra large scale integrated (“ULSI”) circuits. This is due, in large part, to the fact that silicon is the only semiconductor substrate material that can be formed as large-diameter wafers with sufficiently low defect density. Silicon also forms a high-quality oxide (i.e., silicon dioxide), and the quality of the silicon/silicon dioxide interface is also quite high.
It is notable that germanium, while otherwise very desirable as a material for the fabrication of integrated circuits, has not achieved commercial acceptance. This is due to its high cost and low availability, which is a direct consequence of the defect-related low-yield of germanium substrates. This high-defect density results from difficulties with producing bulk germanium substrates.
But the baton might soon be passed from the silicon/silicon dioxide material system to other materials in order to satisfy industry requirements for continued advancements in the performance of integrated circuits and the removal of roadblocks to the continuation of Moore's Law.
More specifically, as node-scaling of ULSI circuits is pushed further into the sub-micron regime, silicon dioxide becomes increasingly less attractive as an interlayer dielectric material (e.g., gate oxide, etc.). In particular, as silicon-based interlayer dielectrics become extremely thin, fundamental problems arise, such as an increase in quantum mechanical tunneling current, a decrease in dielectric breakdown strength, and a decrease in reliability. Furthermore, decreases in the thickness of silicon-based interlayer dielectrics in ULSI electronics will result in increases in capacitance, which cause concomitant increases in RC (interconnect) delays and cross talk. This adversely impacts device speed and power dissipation.
A further issue with the silicon/silicon dioxide material system is that in conventional integrated-circuit processing, a rate-limiting and yield-limiting step is the production of a gate oxide of sufficient quality. In order to produce a high-quality gate oxide, the semiconductor surface is subjected to high temperatures while under vacuum to desorb any native oxide that has formed during prior wafer processing. Once this native oxide is desorbed, a new gate oxide is formed on the newly-cleared surface. As ULSI technology continues to scale further into the sub-micron regime, it will become increasingly difficult and expensive to obtain the gate oxides required.
In order to address these problems, the semiconductor industry has undertaken a search for alternative materials for use as an interlayer dielectric. Suitable alternative materials should exhibit:                i. a dielectric constant (K) higher than that of silicon dioxide;        ii. large conduction and valence band offsets with silicon;        iii. thermal stability and reliability;        iv. high-quality dielectric/semiconductor interface;        v. low impurity concentration; and        vi. manufacturability.        
Single-crystal rare-earth dielectrics are an attractive choice for high-K dielectric materials. Unfortunately, these materials do not naturally occur, nor can they be produced using prior-art growth techniques. On the other hand, amorphous, poly-crystalline, or multi-domain crystalline rare-earth oxides are possible to produce. But these rare-earth oxides are ill-suited for high-performance integrated circuits since they do not exhibit some of the characteristics listed above. In addition, the thickness to which many prior-art rare-earth dielectrics can be grown on silicon is limited.
Rare-earth dielectrics deposited using prior art techniques have not realized single domain, single crystal stoichiometry that enables high performance integrated circuit devices. The inherent limitation of most prior art techniques is a lack of elemental control during deposition. These rare-earth dielectric deposition techniques typically involve the evaporation of constituent rare-earth oxide powders to deposit evaporant on the substrate. Due to the very high melting point of these oxides, coupled with a very low vapor pressure, e-beam evaporation has been the most commonly used technique in the prior art.
Rare-earth dielectrics comprising alkaline-oxide layers are characterized by a negligible conduction band offset relative to silicon. In addition, alkaline-oxide layers on silicon are limited in thickness to approximately 10 monolayers, due to crystal relaxation and defect formation. These alkaline-oxide films, therefore, provide insufficient utility as interlayer dielectric layers in high-performance silicon integrated circuits.
Continued scaling of ULSI into the sub-micron regime is also pushing the limits of the silicon substrate itself. It is widely expected that the future of ULSI will be based on semiconductor-on-insulator wafers that utilize fully-depleted field-effect transistors (FETs) formed in an ultrathin, active layer of silicon. Fully-depleted electronic devices become viable as the thickness of the active layer is reduced below 100 nanometers (nm).
Currently available methods to produce silicon-on-insulator (“SOI”) wafers rely on wafer bonding of oxidized silicon wafers followed by removal of most of one substrate the two substrates to form the active layer. Although several variations of this technology exist, all are incapable of providing ultrathin active layers of sufficient quality for fully-depleted electronics. In addition, the interface quality and impurity concentration of the buried oxide layers is insufficient to support high-performance integrated circuitry. Finally, the complexity of wafer bonding processes used to produce SOI wafers is quite high, which leads to high costs. For these reasons, among any others, the acceptance of SOI wafers by the semiconductor industry has been rather limited.